1. Field of the Invention
The present invention relates to a semiconductor memory apparatus. In particular, the present invention relates to a semiconductor memory apparatus that can adjust a locked loop circuit (DLL (delay-locked loop circuit), PLL (phase-locked loop circuit) and the like) which has functions of generating and adjusting internal clock signals (control clock inside the semiconductor memory apparatus) so as to work at a desired or requested frequency, even if a measuring apparatus is used which has a low operating frequency (frequency used for testing).
Priority is claimed on Japanese Patent Application No. 2007-57252, filed Mar. 7, 2007, the content of which is incorporated herein by reference.
2. Description of the Related Art
In general, an integrated circuit such as SDRAM (synchronous dynamic random access memory), which is a synchronous type, and which inputs an input signal and outputs an output signal while being synchronized with an external clock signal, can work at a high speed. The integrated circuit apparatus inputs/outputs signals while being synchronized with a rising edge of the external clock signal. Therefore, with regard to a high speed semiconductor memory apparatus such as DRAM (dynamic random access memory), there has been a proposal of providing a self-timing control circuit.
The self-timing control circuit is constituted from a locked loop circuit such as DLL (Delays-Locked Loop) or PLL (Phase-Locked Loop). By applying the locked loop circuit, it is possible to generate an inside clock signal (control clock) with stable frequency and phase without being affected by temperature, production process, changes of electric power, and the like (for example, see Patent Documents 1 and 2).
However, a conventional integrated circuit apparatus has a problem. In the problem, it has been difficult to maintain an operational margin of an analog circuit (such as a portion of a delay circuit) of the DLL circuit and the like along with progress of a lower voltage, fineness of a production process and operational speed in recent years, and along with dispersion of VT (voltage thresholds). Therefore, the problem is that, in order to produce the semiconductor circuit apparatus which stably and reliably works, it is necessary to set an allowable range of produced products (allowable range of dispersion of products compared to design specifications) narrow or small.
With regard to such a problem, it is generally known that if it is possible to adjust the analog circuit in detail after producing, it is possible to set the allowable range of produced products and to produce the products which stably and reliably work. Therefore, there has been a desire and demand for adjusting the locked loop circuit in detail after producing the semiconductor memory apparatus.
On the other hand, it has been understood that in order to adjust the locked loop circuit in detail after producing the semiconductor memory apparatus, a fuse-cut (a method of setting a detailed adjusting circuit by applying anti-fuse or the like) in a wafer testing step is effective. However, in general, an apparatus is used which is operated at a slow speed in the wafer testing step. Therefore, there has been a problem in which it was impossible to adjust the locked loop circuits such as DLL and PLL circuits which work at a clock of a high frequency. Therefore, there has been a demand for a solution which can adjust and test operations of the locked loop circuit (DLL circuit or PLL circuit) at a predetermined or desired frequency even if a measuring apparatus is used which has a low operating frequency.    [Patent Document 1] Published Japanese Translation No. 2005-514721 of PCT International Publication    [Patent Document 2] Japanese Unexamined Patent Application, First Publication No. 2005-102120
As described above, there has been a demand for a solution which can adjust the locked loop circuit in detail after producing the semiconductor memory apparatus.
Moreover, there has been a demand for a solution which can adjust the locked loop circuit by using a measuring apparatus which has a low operating frequency (testing frequency).